1. Field of the Invention
The present invention concerns a method of making a MIS semiconductor device.
2. Description of the Related Art
Complementary MOS transistors (hereinafter referred to as CMOS) comprising an N channel MOS field effect transistor (hereinafter referred to as NMOSFET) and a P channel MOS field effect transistor (hereinafter referred to as PMOSFET) are used generally in various devices of LSI constitution including memory LSIs and logic LSIs since they have advantageous features of low power consumption and high speed operation. In such devices, the gate length of FETs will be reduced in the future along with increasing integration degree.
For a gate electrode of PMOSFET, an N+ type electrode has been used like that in NMOSFET in view of the simplicity of the process and high performance due to buried channel type.
On the other hand, in the devices after the deep submicron generation, since the suppression of the short channel effect is difficult in the buried channel type, application of a P+ type gate as a surface channel type is effective.
For manufacturing gates of different polarities such as an N.sup.+ gate for an NMOS transistor and a P.sup.+ type gate for PMOS transistor, N type impurities such as arsenic (As) or phosphorus (P) are doped in a region to form the N.sup.+ type gate, while P-type impurities such as boron (B) or boron difluoride (BF.sub.2) are doped in a region to form a P.sup.+ gate in polycrystal silicon forming the gate electrode. As described above, gates of different conduction types are formed by implanting impurities of different conduction types selectively in most cases.
However, in a case of forming a gate electrode by using a wiring structure in which polycrystal silicon and metal silicide are stacked (polycide structure) or in a case of forming a electrode by using a wiring structure in which polycrystal silicon and metal are stacked, the diffusion rate of impurities in the metal silicide is extremely higher compared with the diffusion speed of impurities in silicon or silicon oxide (by about 4 digits expressed as diffusion coefficient). Accordingly, P.sup.+ type impurities and N.sup.+ type impurities take place inter-diffusion to compensate impurities in polycrystal silicon.
The Fermi level in the polycrystal silicon fluctuates by such an inter-diffusion phenomenon and the gate electrode is depleted upon application of a gate voltage to fluctuate a threshold voltage (hereinafter referred to as Vth) and results in deterioration of device characteristics.
Further, in the P.sup.+ type gate, boron diffuses into a gate oxide film and further reaches as far as a substrate to result in problems such as fluctuation of Vth of MOSFET and lowering of the reliability of the gate oxide film. Particularly, it is known that if fluorine is contained in the polycrystal silicon or gate oxide film, the diffusion rate of boron is increased. Accordingly, it is demanded for optimizing the structure and the making fabrication such that fluorine is not diffused into the polycrystal silicon or gate oxide film.
Then, the subject concerning a dual gate CMOS formed by the related art is to be explained specifically with reference to FIG. 1.
As shown in FIG. 1, a silicon substrate 1 is separated by a field oxide film 2 into an NMOSFET region and a PMOSFET forming region and a gate oxide film 3 is formed on the silicon substrate 1. Then, a tungsten silicide (WSi.sub.x) layer 5 is stacked on the upper surface of a polycrystal silicon layer to form a tungsten polycide structure. In such a tungsten polycide structure, N type (for example phosphorus) impurities are doped in the polycrystal silicon layer 4N and P type (for example, boron) impurities are doped in a polycrystal silicon layer 4P of PMOS transistor.
Then, when a high temperature heat treatment (for example, activating annealing) is applied, phosphorus diffuses through the tungsten silicide layer 5 and diffuses into the polycrystal silicon layer 4P of the P type gate, while boron diffuses through the tungsten silicide layer 5 and diffuses into the polycrystal silicon layer 4N of the N type gate.
Accordingly, Fermi level in the gate electrode fluctuates, and the gate electrode is depleted upon application of the gate voltage, by which vth fluctuates to deteriorate device characteristics. Further, if fluorine is contained in the tungsten silicide layer 5, fluorine diffuses through the crystal grain boundary of the polycrystal silicon layer 4 and reaches the gate oxide film 3 to cause so-called punch through of boron to the silicon substrate 1.
Further, for suppressing inter-diffusion between P.sup.+ type impurities and N.sup.+ type impurities, it has been reported a technique of rendering the composition of tungsten silicide to a so-called silicon rich state with an aim of reducing the diffusion rate in the tungsten silicide layer. This mechanism is adapted to break the chained structure of tungsten and eliminate the diffusion path by rendering the composition of the tungsten silicide to the so-called silicon rich state.
However, if the compositional ratio of silicon in the tungsten silicide layer 5 is excessively increased, resistance value of the tungsten silicide layer 5 is increased, which results in increase of wiring resistance and delay of circuit operation.
Accordingly, the above-mentioned method is not always advantageous.
On the other hand, there is disclosed a method of using polycrystal silicon of large grain size for the polycrystal silicon layer 4, particularly, a method of adopting a dual layer structure for the polycrystal silicon layer 4 and forming the upper polycrystal silicon layer by polycrystal silicon of large grain size. That is, the crystal grain boundary of polycrystal silicon is decreased by increasing the grain size of the polycrystal silicon to suppress diffusion of fluorine or dopant.
Usually, deposition of polycrystal silicon (or amorphous silicon) in the upper layer is conducted directly after the removal of a spontaneous oxide film by using an aqueous fluoric acid solution.
However, if the increase of the grain size in the upper silicon layer is conducted by solid phase growing from amorphous silicon, it causes epitaxial growth in succession of the crystal state of polycrystal silicon in the lower layer. Therefore, the grain size of the polycrystal silicon in the upper silicon layer is not always increased.